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1 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m16-xxx5 april 2004 rev. 5 preliminary* 2mx16 flash module, smd 5962-97610 features ? access times of 90, 120, 150ns ? packaging: ? 56 lead, hermetic ceramic, 0.520" csop (package 207). fits standard 56 ssop footprint. ? 44 pin ceramic soj (package 102)** ? 44 lead ceramic flatpack (package 208)** ? sector architecture ? 32 equal size sectors of 64kbytes each ? any combination of sectors can be erased. also supports full chip erase. ? minimum 100,000 write/erase cycles minimum ? organized as 2mx16; user con gurable as 2 x 2mx8 ? commercial, industrial, and military temperature ranges ? 5 volt read and write. 5v 10% supply. ? low power cmos ? data# polling and toggle bit feature for detection of program or erase cycle completion. ? supports reading or programming data to a sector not being erased. ? built-in decoupling caps and multiple ground pins for low noise operation. ? reset# pin resets internal state machine to the read mode. ? ready/busy (ry#/by#) output for detection of program or erase cycle completion. ? multiple ground pins for low noise operation * this product is under development, is not quali ed or characterized and is subject to change without notice. ** package to be developed. note: for programming information refer to flash programming 16m5 application notes. figure 1 ? pin configurations pin description i/o 0-15 data inputs/outputs a 0-20 address inputs we# write enable cs 1-2 # chip select oe# output enable vcc power supply vss ground ry/by# ready/busy reset# reset block diagram note: 1. ry/by# is an open drain output and should be pulled up to vcc with an external resistor. 2. address compatible with intel 2m8 56 ssop. top view wf2m16-xdax5 56 csop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 cs1# a12 a13 a14 a15 nc cs2# nc a20 a19 a18 a17 a16 v cc gnd i/o6 i/o14 i/o7 i/o15 ry/by# oe# we# nc i/o13 i/o5 i/o12 i/o4 v cc nc #reset a11 a10 a9 a1 a2 a3 a4 a5 a6 a7 gnd a8 v cc i/o9 i/o1 i/o8 i/o0 a0 nc nc nc i/o2 i/o10 i/o3 i/o11 gnd 2m x 8 2m x 8 a 0-20 oe# we# cs 1# cs 2# i/o 0-7 i/o 8-1 reset# ry/by# top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 cs1# a12 a13 a14 a15 nc cs2# nc a20 a19 a18 a17 a16 v cc gnd i/o6 i/o14 i/o7 i/o15 ry/by# oe# we# nc i/o13 i/o5 i/o12 i/o4 v cc nc #reset a11 a10 a9 a1 a2 a3 a4 a5 a6 a7 gnd a8 v cc i/o9 i/o1 i/o8 i/o0 a0 nc nc nc i/o2 i/o10 i/o3 i/o11 gnd wf2m16-xxx5 44 csoj (dl)** 44 flatpack (fl)** ** package to be developed.
2 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m16-xxx5 april 2004 rev. 5 preliminary absolute maximum ratings parameter symbol ratings unit voltage on any pin relative to v ss v t -2.0 to +7.0 v power dissipation p t 8w storage temperature t stg -65 to +125 c short circuit output current i os 100 ma data retention (mil temp) 20 years endurance ? write/erase cycles (mil temp) 100,000 min. cycles recommended dc operating conditions parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v ground v ss 000v input high voltage v ih 2.0 ? v cc + 0.5 v input low voltage v il -0.5 ? +0.8 v operating temperature (mil.) t a -55 ? +125c c operating temperature (ind.) t a -40 ? +85 c dc characteristics - cmos compatible v cc = 5.0v, v ss = 0v, -55c t a +125c parameter symbol conditions min max unit input leakage current i li v cc = 5.5, v in = gnd to v cc 10 a output leakage current i lo v cc = 5.5, v in = gnd to v cc 10 a v cc active current for read (1) i cc1 cs# = v il , oe# = v ih , f = 5mhz 80 ma v cc active current for program or erase (2) i cc2 cs# = v il , oe# = v ih 120 ma v cc standby current i cc3 v cc = 5.5, cs# = v ih , f = 5mhz, reset# = v cc 0.3v 4.0 ma output low voltage v ol i ol = 12.0 ma, v cc = 4.5 0.45 v output high voltage v oh i oh = -2.5 ma, v cc = 4.5 0.85xv cc v low v cc lock-out voltage v lko 3.2 4.2 v capacitance (t a = +25c) parameter symbol conditions max unit oe# capacitance c oe v in = 0v, f = 1.0 mhz 25 pf we# capacitance c we v in = 0v, f = 1.0 mhz 25 pf cs# capacitance c cs v in = 0v, f = 1.0 mhz 15 pf data i/o capacitance c i/o v i/o = 0v, f = 1.0 mhz 15 pf address input capacitance c ad v in = 0v, f = 1.0 mhz 25 pf this parameter is guaranteed by design but not tested. notes: 1. the icc current listed includes both the dc operating current and the frequency dependent component (@ 5mhz). the frequency component typically is less than 2ma/mhz, with oe# at v ih . 2. i cc active while embedded algorithm (program or erase) is in progress. 3. dc test conditions v il = 0.3v, v ih = v cc - 0.3v
3 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m16-xxx5 april 2004 rev. 5 preliminary ac characteristics ? write/erase/program operations - we# controlled v cc = 5.0v, v ss = 0v, -55c t a +125c parameter symbol -90 -120 -150 unit min max min max min max write cycle time t avav t wc 90 120 150 ns chip select setup time t elwl t cs 000ns write enable pulse width t wlwh t wp 45 50 50 ns address setup time t avwl t as 000ns data setup time t dvwh t ds 45 50 50 ns data hold time t whdx t dh 000ns address hold time t wlax t ah 45 50 50 ns write enable pulse width high t whwl t wph 20 20 20 ns duration of byte programming operation (1) t whwh1 300 300 300 s sector erase (2) t whwh2 15 15 15 sec read recovery time before write t gh w l 000 s v cc setup time t vcs 50 50 50 s chip programming time 44 44 44 sec chip erase time (3) 256 256 256 sec output enable hold time (4) t oeh 10 10 10 ns reset# pulse width t rp 500 500 500 ns notes: 1. typical value for t whwh1 is 7 s. 2. typical value for t whwh2 is 1sec. 3. typical value for chip erase time is 32sec. 4. for toggle and data polling. ac characteristics ? read-only operations v cc = 5.0v, v ss = 0v, -55c t a +125c parameter symbol -90 -120 -150 unit min max min max min max read cycle time t avav t rc 90 120 150 ns address access time t avqv t acc 90 120 150 ns chip select access time t elqv t ce 90 120 150 ns output enable to output valid t glqv t oe 40 50 55 ns chip select high to output high z (1) t ehqz t df 20 30 35 ns output enable high to output high z (1) t ghqz t df 20 30 35 ns output hold from addresses, cs# or oe# change, whichever is first t axqx t oh 000ns reset# low to read mode (1) t ready 20 20 20 s 1. guaranteed by design, not tested.
4 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m16-xxx5 april 2004 rev. 5 preliminary ac characteristics ? write/erase/program operations,cs# controlled v cc = 5.0v, v ss = 0v, -55c t a +125c figure 2 ? ac test circuit ac test conditions notes: v z is programmable from -2v to +7v. i ol & i oh programmable from 0 to 16ma. tester impedance z0 = 75 y. v z is typically the midpoint of v oh and v ol . i ol & i oh are adjusted to simulate a typical resistive load circuit.ate tester includes jig capacitance. parameter typ unit input pulse levels v il = 0, v ih = 3.0 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v current source d.u.t. c eff = 50 pf i ol i oh v z 1.5v (bipolar supply) current source parameter symbol -90 -120 -150 unit min max min max min max write cycle time t avav t wc 90 120 150 ns write enable setup time t wlel t ws 000ns chip select pulse width t eleh t cp 45 50 50 ns address setup time t avel t as 000ns data setup time t dveh t ds 45 50 50 ns data hold time t ehdx t dh 000ns address hold time t elax t ah 45 50 50 ns chip select pulse width high t ehel t cph 20 20 20 ns duration of byte programming operation (1) t whwh1 300 300 300 s sector erase time (2) t whwh2 15 15 15 sec read recovery time t ghel 000 s chip programming time 44 44 44 sec chip erase time (3) 256 256 256 sec output enable hold time (4) t oeh 10 10 10 ns notes: 1. typical value for t whwh1 is 7 s. 2. typical value for t whwh2 is 1sec. 3. typical value for chip erase time is 32sec. 4. for toggle and data polling. figure 3 ? reset timing diagram reset# t rp t ready
5 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m16-xxx5 april 2004 rev. 5 preliminary figure 3 ? ac waveforms for read operations addresses fcs1#/fcs2# fdx fdx foe# fwe# outputs high z addresses stable t oe t rc output valid t ce t acc t oh high z t df
6 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m16-xxx5 april 2004 rev. 5 preliminary notes: 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at byte address. 3. d 7 # is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. figure 4 ? write/erase/program operation, we# controlled data# polling cs# oe# we# i/o 7 # i/o out
7 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m16-xxx5 april 2004 rev. 5 preliminary figure 5 ? ac waveforms chip/sector erase operations note: 1. sa is the sector address for sector erase. addresses fcs1#/fcs2# fax fdx foe# fwe# data v cc 5555h 2aaah 2aaah sa 5555h 5555h t wp t cs t vcs 10h/30h 55h 80h 55h aah aah t ah t ghwl t wph t dh t ds t as
8 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m16-xxx5 april 2004 rev. 5 preliminary fig. 6 ? ac waveforms for data# polling during embedded algorithm operations fcs# oe# fwe# t oe t ce t ch t oh d7 d7 = valid data high z d0-d6 = invalid d0-d7 valid data t df d7 d0-d6 t oeh t whwh 1 or 2
9 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m16-xxx5 april 2004 rev. 5 preliminary notes: 1. pa represents the address of the memory location to be programmed. 2. pd represents the data to be programmed at byte address. 3. d 7 # is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates the last two bus cycles of a four bus cycle sequence. we# oe# cs# data# polling figure 7 ? alternate cs# controlled programming operation timings
10 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m16-xxx5 april 2004 rev. 5 preliminary package 208: 44 lead, ceramic flat pack** all linear dimensions are millimeters and parenthetically in inches 28.45 (1.120) 0.26 (0.010) 32.64 (1.285) typ 12.95 (0.510) 0.13 (0.005) 3.81 (0.150) typ 3.18 (0.125) max 0.13 (0.005) 0.05 (0.002) pin 1 identifier 1.27 (0.050) typ 9.90 (0.390) 0.13 (0.005) 26.67 (1.050) typ 43.17 (1.699) 0.39 (0.015) 12.70 (0.500) 0.51 (0.020) 5.08 (0.200) 0.25 (0.010) 0.43 (0.017) 0.05 (0.002) all linear dimensions are millimeters and parenthetically in inches package 102: 44 lead, ceramic soj** 1.27 (0.050) typ 28.70 (1.13) 0.25 (0.010) 26.7 (1.050) typ 11.3 (0.446) 0.2 (0.009) 3.96 (0.156) max 0.2 (0.008) 0.05 (0.002) 9.55 (0.376) 0.25 (0.010) 1.27 (0.050) 0.25 (0.010) 0.89 (0.035) radius typ ** package to be developed. ** package to be developed.
11 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m16-xxx5 april 2004 rev. 5 preliminary figure 8 ? alternate pin configuration for wf2m16w-xdax5 package 207: 56 lead, ceramic sop* all linear dimensions are millimeters and parenthetically in inches * package dimensions subject to change 23.63 (0.930) 0.25 (0.010) 12.96 (0.510) 0.15 (0.006) 0.18 (0.007) 0.03 (0.001) 21.59 (0.850) typ 16.13 (0.635) 0.13 (0.005) 0.25 (0.010) 0.05 (0.002) 0.80 (0.031) typ a 3.57 (0.140) 0.51 (0.020) pin 1 identifier 0 / -4 1.60 (0.063) typ 0.51 (0.020) typ detail "a" see detail "a" 0.51 (0.020) 0.13 (0.005) + 3.43 (0.120) 0.38 (0.015) 0.51 (0.020) 0.13 (0.005) block diagram note: 1. ry/by# is an open drain output and should be pulled up tovcc with an external resistor. 2. address compatible with intel 1m16 56 ssop. 56 csop top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 cs1# a12 a13 a14 a15 nc cs2# a21 a20 a19 a18 a17 a16 vcc gnd i/o6 i/o14 i/o7 i/o15 ry/by# oe# we# nc i/o13 i/o5 i/o12 i/o4 vcc nc reset# a11 a10 a9 a1 a2 a3 a4 a5 a6 a7 gnd a8 vcc i/o9 i/o1 i/o8 i/o0 nc nc nc nc i/o2 i/o10 i/o3 i/o11 gnd 2m x 8 2m x 8 a 1-21 oe# we# cs 1# cs 2# i/o 0-7 i/o 8-15 reset# ry/by# pin description i/o 0-15 data inputs/outputs a 0-21 address inputs we# write enable cs 1-2 # chip select oe# output enable vcc power supply vss ground ry/by# ready/busy reset# reset
12 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs wf2m16-xxx5 april 2004 rev. 5 preliminary w f 2m16 x - xxx x x 5 x lead finish: blank = gold plated leads a = solder dip leads v pp programming voltage 5 = 5v device grade: q = compliant -55c to +125c m = military, 883 screened -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c package type: da = 56 lead csop (package 207) ts standard 56 ssop footprint dl = 44 lead ceramic soj (package 102)* fl = 44 lead ceramic flatpack (package 208)* access time (ns) improvement mark: ? address pinout for 56 csop package w = word wide applications organization of 2m x 16 user con gurable as 2 x 2m x 8 flash white electronic designs corp. ordering information * package to be developed. device type sector size speed package smd no. 2m x 16 flash mcp 150ns 5962-97610 04hxx 2m x 16 flash mcp 120ns 5962-97610 05hxx 2m x 16 flash mcp 90ns 5962-97610 06hxx

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